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ADVANCE INFORMATION
I960(R) RP/RD I/O PROCESSOR AT 3.3 VOLTS
* * * * 33 MHz, 3.3 Volt Version (80960RP 33/3.3) 66 MHz, 3.3 Volt Version (80960RD 66/3.3) - Clock Doubled 80960JF Core Complies with PCI Local Bus Specification Revision 2.1 5 Volt PCI Signalling Environment
s DMA Controller
s High Performance 80960JF Core
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-- Sustained One Instruction/Clock Execution -- 4 Kbyte Two-Way Set-Associative Instruction Cache -- 2 Kbyte Direct-Mapped Data Cache -- Sixteen 32-Bit Global Registers -- Sixteen 32-Bit Local Registers -- Programmable Bus Widths: 8-, 16-, 32-Bit -- 1 Kbyte Internal Data RAM -- Local Register Cache (Eight Available Stack Frames) -- Two 32-Bit On-Chip Timer Units PCI-to-PCI Bridge Unit -- Primary and Secondary PCI Interfaces -- Two 64-Byte Posting Buffers -- Delayed and Posted Transaction Support -- Forwards Memory, I/O, Configuration Commands from PCI Bus to PCI Bus Two Address Translation Units -- Connects Local Bus to PCI Buses -- Inbound/Outbound Address Translation Support -- Direct Outbound Addressing Support Messaging Unit -- Four Message Registers -- Two Doorbell Registers -- Four Circular Queues -- 1004 Index Registers Memory Controller -- 256 Mbytes of 32- or 36-Bit DRAM -- Interleaved or Non-Interleaved DRAM -- Fast Page-Mode DRAM Support -- Extended Data Out and Burst -- Extended Data Out DRAM Support -- Two Independent Banks for SRAM / ROM / Flash (16 Mbytes/Bank; 8- or 32-Bit)
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Three Independent Channels PCI Memory Controller Interface 32-Bit Local Bus Addressing 64-Bit PCI Bus Addressing Independent Interface to Primary and Secondary PCI Buses -- 132 Mbyte/sec Burst Transfers to PCI and Local Buses -- Direct Addressing to and from PCI Buses -- Unaligned Transfers Supported in Hardware -- Two Channels Dedicated to Primary PCI Bus -- One Channel Dedicated to Secondary PCI Bus I/O APIC Bus Interface Unit -- Multiprocessor Interrupt Management for Intel Architecture CPUs (Pentium(R) and Pentium(R) Pro Processors) -- Dynamic Interrupt Distribution -- Multiple I/O Subsystem Support I2C Bus Interface Unit -- Serial Bus -- Master/Slave Capabilities -- System Management Functions Secondary PCI Arbitration Unit -- Supports Six Secondary PCI Devices -- Multi-priority Arbitration Algorithm -- External Arbitration Support Mode Private PCI Device Support -- 352 Ball-Grid Array (HL-PBGA)
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s SuperBGA* Package
(c) INTEL CORPORATION, 1997
September, 1997
Order Number: 273001-002
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. *Third-party brands and names are the property of their respective owners. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 7641 Mt. Prospect IL 60056-764 or call 1-800-548-4725 (c)INTEL CORPORATION, 1997
I960(R) Rx I/O Processor at 3.3 V
1.0 ABOUT THIS DOCUMENT ....................................................................................................................... 1 1.1 Solutions960(R) Program ...................................................................................................................... 1 1.2 Terminology ........................................................................................................................................ 1 1.3 Additional Information Sources ........................................................................................................... 1 2.0 FUNCTIONAL OVERVIEW ....................................................................................................................... 2 2.1 Key Functional Units ........................................................................................................................... 3 2.1.1 PCI-to-PCI Bridge Unit ............................................................................................................. 3 2.1.2 Private PCI Device Support ..................................................................................................... 3 2.1.3 DMA Controller ........................................................................................................................ 3 2.1.4 Address Translation Unit .......................................................................................................... 3 2.1.5 Messaging Unit ........................................................................................................................ 3 2.1.6 Memory Controller ................................................................................................................... 3 2.1.7 I2C Bus Interface Unit .............................................................................................................. 3 2.1.8 I/O APIC Bus Interface Unit ..................................................................................................... 3 2.1.9 Secondary PCI Arbitration Unit ................................................................................................ 4 2.2 I960 Core Features (80960JF) ........................................................................................................... 4 2.2.1 Burst Bus ................................................................................................................................. 5 2.2.2 Timer Unit ................................................................................................................................ 5 2.2.3 Priority Interrupt Controller ....................................................................................................... 5 2.2.4 Faults and Debugging .............................................................................................................. 5 2.2.5 On-Chip Cache and Data RAM ................................................................................................ 5 2.2.6 Local Register Cache ............................................................................................................... 5 2.2.7 Test Features ........................................................................................................................... 5 2.2.8 Memory-Mapped Control Registers ......................................................................................... 6 2.2.9 Instructions, Data Types and Memory Addressing Modes ...................................................... 6 3.0 PACKAGE INFORMATION ....................................................................................................................... 8 3.1 Package Introduction .......................................................................................................................... 8 3.1.1 Functional Signal Definitions .................................................................................................... 8 3.1.2 352-Lead HL-PBGA Package ................................................................................................ 21 3.2 Package Thermal Specifications ...................................................................................................... 31 3.2.1 Thermal Specifications ........................................................................................................... 31 3.2.1.1 Ambient Temperature ............................................................................................... 31 3.2.1.2 Case Temperature .................................................................................................... 31 3.2.1.3 Thermal Resistance .................................................................................................. 31 3.2.2 Thermal Analysis ................................................................................................................... 32 3.3 Sources for Heatsinks and Accessories ........................................................................................... 33 4.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 34 4.1 Absolute Maximum Ratings .............................................................................................................. 34 4.2 VCC5 Pin Requirements (VDIFF) ........................................................................................................ 34 4.3 Targeted DC Specifications .............................................................................................................. 35 4.4 Targeted AC Specifications .............................................................................................................. 37 4.4.1 Relative Output Timings ......................................................................................................... 39 4.4.2 Memory Controller Relative Output Timings .......................................................................... 39 4.4.3 Boundary Scan Test Signal Timings ...................................................................................... 42 4.4.4 APIC Bus Interface Signal Timings ........................................................................................ 42 4.4.5 I2C Interface Signal Timings .................................................................................................. 43 4.5 AC Test Conditions ........................................................................................................................... 44 4.6 AC Timing Waveforms ...................................................................................................................... 44 4.7 Memory Controller Output Timing Waveforms ................................................................................. 48 5.0 BUS FUNCTIONAL WAVEFORMS ........................................................................................................ 55 6.0 DEVICE IDENTIFICATION ON RESET ................................................................................................... 64 iii
I960(R) Rx I/O Processor at 3.3 V
FIGURES Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34.
I960(R) Rx I/O Processor at 3.3 V Functional Block Diagram .......................................................... 2 80960JF Core Block Diagram ........................................................................................................ 4 352L HL-PBGA Package Diagram (Top and Side View) ............................................................. 21 352L HL-PBGA Package Diagram (Bottom View) ....................................................................... 22 Thermocouple Attachment - No Heat Sink .................................................................................. 31 Thermocouple Attachment - With Heat Sink ................................................................................ 31 VCC5 Current-Limiting Resistor ................................................................................................... 34 AC Test Load ............................................................................................................................... 44 S_CLK, TCLK Waveform ............................................................................................................. 44 TOV Output Delay Waveform ....................................................................................................... 45 TOF Output Float Waveform ......................................................................................................... 45 TIS and TIH Input Setup and Hold Waveform ............................................................................... 46 TLXL and TLXA Relative Timings Waveform ................................................................................. 46 DT/R# and DEN# Timings Waveform .......................................................................................... 47 I2C Interface Signal Timings ........................................................................................................ 47 Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus ... 48 Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus . 49 FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States .......................................... 50 FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States ........................................... 51 EDO DRAM, Read Cycle ............................................................................................................. 52 EDO DRAM, Write Cycle ............................................................................................................. 52 BEDO DRAM, Read Cycle ........................................................................................................... 53 BEDO DRAM, Write Cycle ........................................................................................................... 53 32-Bit Bus, SRAM Read Accesses with 0 Wait States ................................................................ 54 32-Bit Bus, SRAM Write Accesses with 0 Wait States ................................................................ 54 Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus .............. 55 Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus ...................... 56 Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ................................ 57 Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus ........................ 58 Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus ................................................................................................................ 59 Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus ........................................................................... 60 HOLD/HOLDA Waveform For Bus Arbitration ............................................................................. 61 80960 Core Cold Reset Waveform .............................................................................................. 62 80960 Local Bus Warm Reset Waveform .................................................................................... 63
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TABLES Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32.
Related Documentation ................................................................................................................. 1 80960Rx Instruction Set ................................................................................................................ 7 Signal Type Definition .................................................................................................................... 8 Signal Descriptions ........................................................................................................................ 9 Power Requirement, Processor Control and Test Signal Descriptions ....................................... 13 Interrupt Unit Signal Descriptions .................................................................................... ............ 14 PCI Signal Descriptions ............................................................................................... ................ 15 Memory Controller Signal Descriptions ....................................................................................... 18 DMA, APIC, I2C Units Signal Descriptions .................................................................................. 19 Clock Signal ................................................................................................................................. 20 ICE Signal Descriptions ............................................................................................................... 20 352-Lead HL-PBGA Package -- Signal Name Order (Sheet 1 of 4) ........................................... 23 352-Lead HL-PBGA Pinout -- Ballpad Number Order (Sheet 1 of 4) ......................................... 27 352-Lead HL-PBGA Package Thermal Characteristics ............................................................... 32 Heatsink Information .................................................................................................................... 33 Operating Conditions ................................................................................................................... 34 VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) ....................................... 34 DC Characteristics ....................................................................................................................... 35 ICC Characteristics ....................................................................................................................... 36 Input Clock Timings ..................................................................................................................... 37 Synchronous Output Timings ...................................................................................................... 37 Synchronous Input Timings ......................................................................................................... 38 Relative Output Timings .............................................................................................................. 39 Fast Page Mode Non-interleaved DRAM Output Timings ........................................................... 39 Fast Page Mode Interleaved DRAM Output Timings ................................................................... 40 EDO DRAM Output Timings ........................................................................................................ 40 BEDO DRAM Output Timings ...................................................................................................... 41 SRAM/ROM Output Timings ........................................................................................................ 41 Boundary Scan Test Signal Timings ............................................................................................ 42 APIC Bus Interface Signal Timings .............................................................................................. 42 I2C Interface Signal Timings ........................................................................................................ 43 Processor Device ID Register - PDIDR ...................................................................................... 64
I960(R) Rx I/O Processor at 3.3 V
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I960(R) Rx I/O Processor at 3.3 V
1.0
ABOUT THIS DOCUMENT
1.1
Solutions960(R) Program
This is the ADVANCE INFORMATION data sheet for the low-power (3.3 V) versions of Intel's I960(R) Rx I/O Processor family, including: * 80960RD 66/3.3 * 80960RP 33/3.3 Throughout this document, these family members are referred to as 80960Rx when the information is common to both. For product-specific information, such as electrical characteristics, the family member names are used. This does not contain specifications for the 5 Volt version (80960RP 33/5.0). For specifications on that product, refer to the I960(R) RP I/O Processor Data Sheet (272737). This data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the I960(R) RP Microprocessor User's Guide (272736).
Intel's Solutions960(R) program features a wide variety of development tools which support the I960 processor family. Many of these tools are developed by partner companies; some are developed by Intel, such as profile-driven optimizing compilers. For more information on these products, contact your local Intel representative.
1.2
Terminology
In this document, the following terms are used: * local bus refers to the 80960Rx's internal local bus, not the PCI local bus. * Primary and Secondary PCI buses are the 80960Rx's internal PCI buses which conform to PCI SIG specifications. * 80960 core refers to the 80960JF processor which is integrated into the 80960Rx.
1.3
Additional Information Sources
Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect IL 60056-7641 1-800-879-4683
Table 1. Related Documentation Document Title I960(R) RP Microprocessor User's Guide I960(R) RP Processor: A Single-Chip Intelligent I/O Subsystem Technical Brief I960(R) Jx Microprocessor User's Guide 80960RP Specification Update PCI Local Bus Specification Revision 2.1 PCI-to-PCI Bridge Architecture Specification Revision 1.0 I2C Peripherals for Microcontrollers Order / Contact Intel Order # 272736 Intel Order # 272738 Intel Order # 272483 Intel Order # 272918 PCI Special Interest Group 1-800-433-5177 PCI Special Interest Group 1-800-433-5177 Philips Semiconductor
ADVANCE INFORMATION
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I960(R) Rx I/O Processor at 3.3 V
2.0
FUNCTIONAL OVERVIEW
As indicated in Figure 1, the 80960Rx combines many features with the 80960JF to create an intelligent I/O processor. Subsections following the figure briefly describe the main features; for detailed functional descriptions, refer to the I960(R) RP Microprocessor User's Guide (272736). The PCI bus is an industry standard, high performance, low latency system bus that operates up to 132 Mbyte/s. The 80960Rx, a multi-function PCI device, is fully compliant with the PCI Local Bus Specification Revision 2.1. Function 0 is the PCI-toPCI bridge unit; Function 1 is the address translation unit.
The PCI-to-PCI bridge unit is the connection path between two independent 32-bit PCI buses and provides the ability to overcome PCI electrical load limits. The addition of the I960 core processor brings intelligence to the bridge. The 80960Rx, object code compatible with the I960 core processor, is capable of sustained execution at the rate of one instruction per clock. The local bus, a 32-bit multiplexed burst bus, is a high-speed interface to system memory and I/O. A full complement of control signals simplifies the connection of the 80960Rx to external components. Physical and logical memory attributes are programmed via memory-mapped control registers (MMRs), an extension not found on the I960 Kx, Sx or Cx processors. Physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment.
Local Memory
I2C Serial Bus
I/O APIC Bus
Memory Controller
I960(R) JF
Core Processor I2C Bus Interface Unit I/O APIC Bus Interface Unit Internal Arbitration
Local Bus Primary ATU Address Translation Unit Message Unit
Secondary ATU Address Translation Unit
Two DMA Channels
One DMA Channel
PCI-to-PCI Bridge Unit Secondary PCI Bus Primary PCI Bus Secondary PCI Arbitration Unit
Figure 1. I960(R) Rx I/O Processor at 3.3 V Functional Block Diagram
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I960(R) Rx I/O Processor at 3.3 V
2.1
2.1.1
Key Functional Units
PCI-to-PCI Bridge Unit
Address translation is controlled through programmable registers accessible from both the PCI interface and the 80960 core. Dual access to registers allows flexibility in mapping the two address spaces. 2.1.5 Messaging Unit
The PCI-to-PCI bridge unit (referred to as "bridge") connects two independent PCI buses. It is fully compliant with the PCI-to-PCI Bridge Architecture Specification Revision 1.0 published by the PCI Special Interest Group. It allows certain bus transactions on one PCI bus to be forwarded to the other PCI bus. Dedicated data queues support high performance bandwidth on the PCI buses. The I960(R) Rx I/O Processor at 3.3 V supports PCI 64-bit Dual Address Cycle (DAC) addressing. The bridge has dedicated PCI configuration space that is accessible through the primary PCI bus. 2.1.2 Private PCI Device Support
The Messaging Unit (MU) provides data transfer between the PCI system and the 80960Rx. It uses interrupts to notify each system when new data arrives. The MU has four messaging mechanisms. Each allows a host processor or external PCI device and the 80960Rx to communicate through message passing and interrupt generation. The four mechanisms are Message Registers, Doorbell Registers, Circular Queues, and Index Registers. 2.1.6 Memory Controller
A key design feature is that the 80960Rx explicitly supports private PCI devices on the secondary PCI bus without being detected by PCI configuration software. The bridge and Address Translation Unit work together to hide private devices from PCI configuration cycles and allow these devices to use a private PCI address space. The Address Translation Unit uses normal PCI configuration cycles to configure these devices. 2.1.3 DMA Controller
The Memory Controller allows direct control of external memory systems, including DRAM, SRAM, ROM and Flash Memory. It provides a direct connect interface to memory that typically does not require external logic. It features programmable chip selects, a wait state generator and byte parity. External memory can be configured as PCI addressable memory or private processor memory. 2.1.7 I2C Bus Interface Unit
The DMA Controller supports low-latency, highthroughput data transfers between PCI bus agents and 80960 local memory. Three separate DMA channels accommodate data transfers: two for primary PCI bus, one for the secondary PCI bus. The DMA Controller supports chaining and unaligned data transfers. It is programmable only through the I960 core processor. 2.1.4 Address Translation Unit
The I2C (Inter-Integrated Circuit) Bus Interface Unit allows the 80960 core to serve as a master and slave device residing on the I2C bus. The I2C bus is a serial bus developed by Philips Semiconductor consisting of a two pin interface. The bus allows the 80960Rx to interface to other I2C peripherals and microcontrollers for system management functions. It requires a minimum of hardware for an economical system to relay status and reliability information on the I/O subsystem to an external device. For more information, see I2C Peripherals for Microcontrollers (Philips Semiconductor) 2.1.8 I/O APIC Bus Interface Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 80960Rx local memory. The 80960Rx has direct access to both PCI buses. The ATU supports transactions between PCI address space and 80960Rx address space.
The I/O APIC Bus Interface Unit provides an interface to the three-wire Advanced Programmable Interrupt Controller (APIC) bus that allows I/O APIC emulation in software. Interrupt messages can be sent on the bus and EOI messages can be received.
ADVANCE INFORMATION
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I960(R) Rx I/O Processor at 3.3 V
2.1.9
Secondary PCI Arbitration Unit
* Independent Multiply/Divide Unit * Efficient instruction pipeline minimizes pipeline break latency * Register and resource scoreboarding allow overlapped instruction execution * 128-bit register bus speeds local register caching * 4 Kbyte two-way set-associative, integrated instruction cache * 2 Kbyte direct-mapped, integrated data cache * 1 Kbyte integrated data RAM delivers zero wait state program data The 80960 core operates out of its own 32-bit address space, which is independent of the PCI address space. The local bus memory can be: * Made visible to the PCI address space * Kept private to the 80960 core * Allocated as a combination of the two
The Secondary PCI Arbitration Unit provides PCI arbitration for the secondary PCI bus. It includes a fairness algorithm with programmable priorities and six PCI Request and Grant signal pairs. This arbitration unit can also be disabled to allow for external arbitration.
2.2
I960 Core Features (80960JF)
The processing power of the 80960Rx comes from the 80960JF processor core. The 80960JF is a new, scalar implementation of the 80960 Core Architecture. Figure 2 shows a block diagram of the 80960JF Core processor. Factors that contribute to the 80960 family core's performance include: * Single-clock execution of most instructions
S_CLK PLL, Clocks, Power Mgmt Instruction Cache
32-bit buses address / data
Physical Region Configuration Bus Control Unit Bus Request Queues
Control
4 Kbyte Two-Way Set Associative
TAP 5 Boundary Scan Controller Instruction Sequencer
Constants Control
Address/ Data Bus 32
Two 32-Bit Timers Interrupt Port 9
8-Set Local Register Cache Multiply Divide Unit
Programmable Interrupt Controller Execution and Address Generation Unit
Effective Address SRC1 SRC2 SRC1 SRC2 DST DST
Memory Interface Unit
Memory-Mapped Register Interface
128 Global / Local Register File
SRC1 SRC2 DST
32-bit Addr 32-bit Data SRC1 DST
1 Kbyte Data RAM
3 Independent 32-Bit SRC1, SRC2, and DST Buses
2 Kbyte Direct Mapped Data Cache
Figure 2. 80960JF Core Block Diagram
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I960(R) Rx I/O Processor at 3.3 V
2.2.1
Burst Bus
* Register frames for high-priority interrupt handlers can be cached on-chip * The interrupt stack can be placed in cacheable memory space 2.2.4 Faults and Debugging
A 32-bit high-performance bus controller interfaces the 80960Rx to external memory and peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus at the rate of up to four 32bit words per six clock cycles. The external address/data bus is multiplexed. Users may configure the 80960Rx's bus controller to match an application's fundamental memory organization. Physical bus width is programmable for up to eight regions. Data caching is programmed through a group of logical memory templates and a defaults register. The Bus Control Unit's features include: * Multiplexed external bus minimizes pin count * 32-, 16- and 8-bit bus widths simplify I/O interfaces * External ready control for address-to-data, data-todata and data-to-next-address wait state types * Little endian byte ordering * Unaligned bus accesses performed transparently * Three-deep load/store queue decouples the bus from the 80960 core Upon reset, the 80960Rx conducts an internal self test. Before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the Initialization Boot Record. 2.2.2 Timer Unit
The 80960Rx employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. The processor also has built-in debug capabilities. Via software, the 80960Rx may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions can generate trace events explicitly in the instruction stream. Hardware breakpoint registers are also available to trap on execution and data addresses. 2.2.5 On-Chip Cache and Data RAM
Memory subsystems often impose substantial wait state penalties. The 80960Rx integrates considerable storage resources on-chip to decouple CPU execution from the external bus. It also includes a 4 Kbyte instruction cache, a 2 Kbyte data cache and 1 Kbyte data RAM. 2.2.6 Local Register Cache
The timer unit (TU) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. Each is programmed by use of the Timer Unit registers. These memorymapped registers are addressable on 32-bit boundaries. The timers have a single-shot mode and autoreload capabilities for continuous operation. Each timer has an independent interrupt request to the 80960Rx's interrupt controller. The TU can generate a fault when unauthorized writes from user mode are detected. 2.2.3 Priority Interrupt Controller
The 80960Rx rapidly allocates and deallocates local register sets during context switches. The processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. 2.2.7 Test Features
The 80960Rx incorporates numerous features that enhance the user's ability to test both the processor and the system to which it is attached. These features include ONCE (On-Circuit Emulation) mode and Boundary Scan (JTAG). The 80960Rx provides testability features compatible with IEEE Standard Test Access Port and Boundary Scan Architecture (IEEE Std. 1149.1).
Low interrupt latency is critical to many embedded applications. As part of its highly flexible interrupt mechanism, the 80960Rx exploits several techniques to minimize latency: * Interrupt vectors and interrupt handler routines can be reserved on-chip
ADVANCE INFORMATION
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I960(R) Rx I/O Processor at 3.3 V
One of the boundary scan instructions, HIGHZ, forces the processor to float all its output pins (ONCE mode). ONCE mode can also be initiated at reset without using the boundary scan mechanism. ONCE mode is useful for board-level testing. This feature allows a mounted 80960Rx to electrically "remove" itself from a circuit board. This mode allows system-level testing where a remote tester can exercise the processor system. The test logic does not interfere with component or system behavior and ensures that components function correctly, and also the connections between various components are correct. The JTAG Boundary Scan feature is an alternative to conventional "bed-of-nails" testing. It can examine connections that might otherwise be inaccessible to a test system. 2.2.8 Memory-Mapped Control Registers
* Five Register Indirect modes * Index with displacement mode * IP with displacement mode Table 2 shows the available instructions.
The 80960Rx is compliant with 80960 family architecture and has the added advantage of memorymapped, internal control registers not found on the 80960Kx, Sx or Cx processors. This feature provides software an interface to easily read and modify internal control registers. Each memory-mapped, 32-bit register is accessed via regular memory-format instructions. The processor ensures that these accesses do not generate external bus cycles. 2.2.9 Instructions, Data Types and Memory Addressing Modes
As with all 80960 family processors, the 80960Rx instruction set supports several different data types and formats: * Bit * Bit fields * Integer (8-, 16-, 32-, 64-bit) * Ordinal (8-, 16-, 32-, 64-bit unsigned integers) * Triple word (96 bits) * Quad word (128 bits) The 80960Rx provides a full set of addressing modes for C and assembly: * Two Absolute modes
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I960(R) Rx I/O Processor at 3.3 V
Table 2. 80960Rx Instruction Set Data Movement Load Store Move Conditional Select Load Address Add Subtract Multiply Divide Remainder Modulo Shift Extended Shift Extended Multiply Extended Divide Add with Carry Subtract with Carry Conditional Add Conditional Subtract Rotate Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark Processor Management Flush Local Registers Modify Arithmetic Controls Modify Process Controls Halt System Control Cache Control Interrupt Control Atomic Atomic Add Atomic Modify Branch Unconditional Branch Conditional Branch Compare and Branch Call Call Extended Call System Return Branch and Link Call/Return Fault Conditional Fault Synchronize Faults Arithmetic And Not And And Not Or Exclusive Or Not Or Or Not Nor Exclusive Nor Not Nand Logical Bit, Bit Field and Byte Set Bit Clear Bit Not Bit Alter Bit Scan For Bit Span Over Bit Extract Modify Scan Byte for Equal Byte Swap
ADVANCE INFORMATION
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I960(R) Rx I/O Processor at 3.3 V
3.0 3.1
PACKAGE INFORMATION
Symbol
Table 3. Signal Type Definition Description Input signal only. Output signal only. Signal can be either an input or output. Open Drain signal. Signal must be connected as described. Synchronous. Inputs must meet setup and hold times relative to S_CLK. S(E) Edge sensitive input S(L) Level sensitive input A (...) Asynchronous. Inputs may be asynchronous relative to S_CLK. A(E) Edge sensitive input A(L) Level sensitive input R (...) While the P_RST# signal is asserted, the signal: R(1) is driven to VCC R(0) is driven to VSS R(Q) is a valid output R(Z) Floats R(H) is pulled up to VCC R(X) is driven to an unknown state H (...) While the 80960Rx is in the hold state, the signal: H(1) is driven to VCC H(0) is driven to VSS H(Q) Maintains previous state or continues to be a valid output H(Z) Floats P (...) While the 80960Rx is halted, the signal: P(1) is driven to VCC P(0) is driven to VSS P(Q) Maintains previous state or continues to be a valid output K (...) While the Secondary PCI Bus is being parked, the signal: K(Z) Floats K(Q) Maintains previous state or continues to be a valid output
Package Introduction
I O I/O OD - S (...)
The 80960Rx is offered in a SuperBGA* Ball Grid Array (HL-PBGA) package. This is a perimeter array package with four rows of ball connections in the outer area of the package. See Figure 4, 352L HLPBGA Package Diagram (Bottom View) (pg. 22). Section 3.1.1, Functional Signal Definitions describes signal function; Section 3.1.2, 352-Lead HL-PBGA Package defines the signal and ball locations. 3.1.1 Functional Signal Definitions
Table 3 presents the legend for interpreting the Type Field in the following tables. Table 4 defines signals associated with the bus interface. Table 5 defines signals associated with basic control and test functions. Table 6 defines signals associated with the Interrupt Unit. Table 7 defines PCI signals. Table 8 defines Memory Controller signals. Table 9 defines DMA, APIC and I2C signals. Table 10 defines clock signals. Table 11 defines ICE signals.
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ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 1 of 5) NAME AD31:0 TYPE I/O S(L) R(Z) H(Z) P(Q) DESCRIPTION ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32bit data to and from memory. During an address (Ta) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate SIZE; see below). During a data (Td) cycle, read or write data is present on one or more contiguous bytes, comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations, unused signals are driven to determinate values. SIZE, which comprises bits 0-1 of the AD lines during a Ta cycle, specifies the number of data transfers during the bus transaction on the local bus. When the DMA or ATUs initiate data transfers, transfer size shown below is not valid. AD1 0 0 1 1 AD0 0 1 0 1 Bus Transfers 1 Transfer 2 Transfers 3 Transfers 4 Transfers
When the 80960Rx enters Halt mode and the previous bus operation was: * write -- AD31:2 are driven with the last data value on the AD bus. * read -- AD31:2 are driven with the last address value on the AD bus. Typically, AD1:0 reflect the SIZE information of the last bus transaction (either instruction fetch or load/store) that was executed before entering Halt mode. ADS# O R(1) H(Z) P(1) O R(0) H(Z) P(0) O H(Z) P(1) ADDRESS STROBE indicates a valid address and the start of a new bus access. The processor asserts ADS# for the entire Ta cycle. External bus control logic typically samples ADS# at the end of the cycle. ADDRESS LATCH ENABLE indicates the transfer of a physical address. ALE is asserted during a Ta cycle and deasserted before the beginning of the Td state. It is active HIGH and floats to a high impedance state during a hold cycle (Th). BURST LAST indicates the last transfer in a bus access. BLAST# is asserted in the last data transfer of burst and non-burst accesses. BLAST# remains active while wait states are detected via the LRDYRCV# or RDYRCV# signal on the memory controller. BLAST# becomes inactive after the final data transfer in a bus cycle. BLAST# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = Last Data Transfer 1 = Not the Last Data Transfer
ALE
BLAST#
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I960(R) Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 2 of 5) NAME BE3:0# TYPE O R(1) H(Z) P(1) DESCRIPTION BYTE ENABLES select which of up to four data bytes on the bus participate in the current bus access. Byte enable encoding depends on the bus width of the memory region accessed:
32-bit bus: BE3# enables data on AD31:24 BE2# enables data on AD23:16 BE1# enables data on AD15:8 BE0# enables data on AD7:0 16-bit bus: BE3# becomes Byte High Enable (enables data on AD15:8) BE2# is not used (state is high) BE1# becomes Address Bit 1 (A1) (increments with the assertion of LRDY# or RDYRCV#) BE0# becomes Byte Low Enable (enables data on AD7:0) 8-bit bus: BE3# is not used (state is high) BE2# is not used (state is high) BE1# becomes Address Bit 1 (A1) (increments with the assertion of LRDY# or RDYRCV#) BE0# becomes Address Bit 0 (A0) (increments with the assertion of LRDY# or RDYRCV#) The processor asserts byte enables, byte high enable and byte low enable during Ta. Since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst (32-bit bus only) from the I960 core processor; they do toggle for DMA and ATU cycles. They remain active through the last Td cycle.
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. DEN# is used with DT/R# to provide control for data transceivers connected to the data bus. DEN# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = Data Cycle 1 = Not a Data Cycle
DEN#
O H(Z) P(1)
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I960(R) Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 3 of 5) NAME D/C#/ RST_MODE# TYPE I/O R(H) H(Z) P(Q) DESCRIPTION DATA/CODE/RESET_MODE indicates that a bus access is a data access or an instruction access. D/C# has the same timing as W/R#. 0 = Instruction Access 1 = Data Access The RST_MODE# signal is sampled at Primary PCI bus reset to determine whether the 80960 core is to be held in reset. When RST_MODE# is high, the 80960Rx begins initialization immediately following the deassertion of P_RST. When RST_MODE is low, the 80960 core remains in reset until the 80960 core reset bit is cleared in the extended bridge control register. This signal has a weak internal pullup that is active during reset to ensure normal operation when the signal is left unconnected. 0 = RST_MODE enabled 1 = RST_MODE not enabled While the 80960 core is in reset, all peripherals may be accessed from the primary or secondary PCI buses depending on the status of the WIDTH/HLTD1/RETRY/ signal. DT/R# O R(0) H(Z) P(Q) DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and from the address/data bus. It is low during Ta and Tw/Td cycles for a read; it is high during Ta and Tw/Td cycles for a write. DT/R# never changes state when DEN# is asserted. 0 = Receive 1 = Transmit LOCK#/ONCE# I/O S(L) R(H) H(Z) P(Q) BUS LOCK indicates that an atomic read-modify-write operation is in progress. The LOCK# output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. The processor does not grant HOLDA while asserting LOCK#. This prevents external agents from accessing memory involved in semaphore operations. 0 = Atomic Read-Modify-Write in Progress 1 = No Atomic Read-Modify-Write in Progress ONCE MODE: The processor samples the ONCE input during reset. When ONCE# is asserted LOW at the end of reset, the processor enters ONCE mode, stops all clocks and floats all output signals. LOCK#/ONCE# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = ONCE Mode Enabled 1 = ONCE Mode Not Enabled LRDYRCV# O R(1) H(Q) P(Q) LOCAL READY/RECOVER, generated by the 80960Rx's memory controller unit, is an output version of the READY/RECOVER (RDYRCV#) signal. Refer to the RDYRCV# signal description.
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I960(R) Rx I/O Processor at 3.3 V
Table 4. Signal Descriptions (Sheet 4 of 5) NAME HOLD TYPE I S(L) DESCRIPTION HOLD is a request from an external bus master to acquire the bus. When the processor receives HOLD and grants bus control to another master, it asserts HOLDA, floats the address/data and control lines and enters the Th state. When HOLD is deasserted, the processor deasserts HOLDA and enters either the Ti or Ta state, resuming control of the address/data and control lines. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration (pg. 61). 0 = No Hold Request 1 = Hold Requested HOLDA O R(0) H(1) P(Q) HOLD ACKNOWLEDGE indicates to an external bus master that the processor has relinquished bus control. The processor can grant HOLD requests and enter the Th state and while halted as well as during regular operation. See Figure 32, HOLD/HOLDA Waveform For Bus Arbitration (pg. 61). 0 = No Hold Acknowledged 1 = Hold Acknowledged RDYRCV# I S(L) READY/RECOVER is only used in systems that use an external memory controller (and do not use the 80960Rx's memory controller unit). This signal indicates that data on AD lines can be sampled or removed. When RDYRCV# is not asserted during a Td cycle, the Td cycle extends to the next cycle by inserting a wait state (Tw). 0 = Sample Data 1 = Do Not Sample Data RDYRCV# has an alternate function during the recovery (Tr) state. The processor continues to insert recovery states until it samples the signal HIGH. This gives slow external devices more time to float their buffers before the processor drives addresses. 0 = Insert Wait States 1 = Recovery Complete When using the internal memory controller, connect this signal to VCC through a 2.7 K resistor. W/R# O R(0) H(Z) P(Q) I/O R(H) H(Z) P(Q) WRITE/READ specifies during a Ta cycle whether the operation is a write or read. It is latched on-chip and remains valid during Td cycles. 0 = Read 1 = Write WIDTH denotes the physical memory attributes for a bus transaction in conjunction with WIDTH/HLTD1/RETRY: WIDTH/HLTD1/RETRY 0 0 1 1 WIDTH/HLTD0 0 1 0 1 8 Bits Wide 16 Bits Wide 32 Bits Wide Undefined
WIDTH/ HLTD0
WIDTH/HLTD0 For proper operation, do not connect this signal to ground. This signal has a weak internal pullup which is active during reset to ensure normal operation. HLTD0 signal name has no function in the 80960Rx; the signal name is included for 80960JF naming convention compatibility. 12
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Table 4. Signal Descriptions (Sheet 5 of 5) NAME WIDTH/ HLTD1/ RETRY TYPE I/O R(H) H(Z) P(Q) DESCRIPTION WIDTH denotes the physical memory attributes for a bus transaction in conjunction with the WIDTH/HLTD0 signal. Refer to description above. RETRY is sampled at Primary PCI bus reset to determine when the Primary PCI interface is disabled. When high, the Primary PCI interface disables PCI configuration cycles by signaling a RETRY until the Extended Bridge Control Register's Configuration Cycle Disable bit is cleared. When low, the Primary PCI interface allows configuration cycles to occur. WIDTH/HLTD1/RETRY has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. HLTD1 signal name has no function in the 80960Rx; the signal name is included for 80960JF naming convention compatibility. Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 1 of 2) NAME FAIL# TYPE O R(0) H(Q) DESCRIPTION FAIL indicates a failure of the processor's built-in self-test performed during initialization. FAIL# is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests: * When self-test passes, the processor deasserts FAIL# and commences operation from user code. * When self-test fails, the processor asserts FAIL# and then stops executing. Selftest failing does not cause the bridge to stop execution. 0 = Self Test Failed 1 = Self Test Passed L_RST# STEST O I S(L) LOCAL BUS RESET notifies external devices that the local bus has reset. SELF TEST enables or disables the processor's internal self-test feature at initialization. STEST is examined at the end of P_RST#. When STEST is asserted, the processor performs its internal self-test and the external bus confidence test. When STEST is deasserted, the processor performs only the external bus confidence test. 0 = Self Test Disabled 1 = Self Test Enabled TCK I TEST CLOCK is a CPU input that provides the clocking function for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. TEST DATA INPUT is the serial input signal for JTAG. TDI is sampled on the rising edge of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port. This signal has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. TEST DATA OUTPUT is the serial output signal for JTAG. TDO is driven on the falling edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At other times, TDO floats. TEST MODE SELECT is sampled at the rising edge of TCK to select the operation of the test logic for IEEE 1149.1 Boundary Scan testing. This signal has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected.
TDI
I S(L)
TDO
O R(Q) H(Q) P(Q) I S(L)
TMS
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I960(R) Rx I/O Processor at 3.3 V
Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet 2 of 2) NAME TRST# TYPE I A(L) DESCRIPTION TEST RESET asynchronously resets the Test Access Port (TAP) controller function of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan feature, connect a pulldown resistor (1.5 K) between this signal and VSS. When TAP is not used, this signal must be connected to VSS; however, no resistor is required. The signal has a weak internal pullup which must be overcome during reset to ensure normal operation. POWER. Connect to a 3.3 Volt VCC board plane. 5 VOLT REFERENCE VOLTAGE. Input is the reference voltage for the 5 V-tolerant I/O buffers. Connect this signal to +5 V for use with signals which exceed 3.3 V. When all inputs are from 3.3 V components, connect this signal to 3.3 V. GROUND. Connect to a VSS board plane. NO CONNECT. Do not make electrical connections to these balls. PLL POWER. For external connection to a 3.3 V VCC board plane. Power to PLLs requires external filtering.
VCC VCC5
- -
VSS N.C. VCCPLL3:1
- - I
Table 6. Interrupt Unit Signal Descriptions NAME NMI# TYPE I A(L) I A(L) DESCRIPTION NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI# is the highest priority interrupt source and is level-detect. When NMI# is unused, it is recommended that you connect it to VCC . SECONDARY PCI BUS INTERRUPT1 requests an interrupt. S_INTx# assertion and deassertion is asynchronous to S_CLK. A device asserts S_INTx# when requesting attention from its device driver. When S_INTx# is asserted, it remains asserted until the device driver clears the pending request. S_INTx# Interrupts are level sensitive. EXTERNAL INTERRUPT. External devices use this signal to request an interrupt service. These signals operate in dedicated mode, where each signal is assigned a dedicated interrupt level. The S_INT[A:D]#/XINT3:0# signals can be directed as follows: Sec. PCI S_INTA# S_INTB# S_INTC# S_INTD# XINT7:4# I A(L) Primary PCI 80960 Core Processor or or or or XINT0# XINT1# XINT2# XINT3#
S_INT[A:D]#/ XINT3:0#

P_INTA# P_INTB# P_INTC# P_INTD#
EXTERNAL INTERRUPT. External devices use this signal to request an interrupt service. These signals operate in dedicated mode, where each signal is assigned a dedicated interrupt level.
NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision 2.1 for a more complete definition.
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I960(R) Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 1 of 3) NAME P_AD31:0 TYPE I/O K(Q) R(Z) I/O K(Q) R(Z) I/O R(Z) P_FRAME# I/O R(Z) P_GNT# P_IDSEL I R(Z) I S(L) O OD R(Z) PRIMARY PCI BUS GRANT indicates to the agent that access to the bus has been granted. This is a point-to-point signal. PRIMARY PCI BUS INITIALIZATION DEVICE SELECT selects the 80960Rx during a Configuration Read or Write command on the primary PCI bus. PRIMARY PCI BUS INTERRUPT requests an interrupt. The assertion and deassertion of P_INTx# is asynchronous to S_CLK. A device asserts its P_INTx# line when requesting attention from its device driver. Once the P_INTx# signal is asserted, it remains asserted until the device driver clears the pending request. P_INTx# Interrupts are level sensitive. PRIMARY PCI BUS INITIATOR READY indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. PRIMARY PCI BUS LOCK indicates an atomic operation that may require multiple transactions to complete. PRIMARY PCI BUS PARITY. This signal ensures even parity across P_AD31:0 and P_C/BE3:0. All PCI devices must provide a parity signal. PRIMARY PCI BUS PARITY ERROR is used for reporting data parity errors during all PCI transactions except a special cycle. PRIMARY PCI BUS REQUEST indicates to the arbiter that this agent desires use of the bus. This is a point to point signal. DESCRIPTION1 PRIMARY PCI ADDRESS/DATA is the primary multiplexed PCI address and data bus. PRIMARY PCI BUS COMMAND and BYTE ENABLE signals are multiplexed on the same PCI signals. During an address phase, P_C/BE3:0# define the bus command. During a data phase, P_C/BE3:0# are used as byte enables. PRIMARY PCI BUS DEVICE SELECT is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. PRIMARY PCI BUS CYCLE FRAME is asserted to indicate the beginning and duration of an access on the Primary PCI bus.
P_C/BE3:0#
P_DEVSEL#
P_INT[A:D]#
P_IRDY# P_LOCK# P_PAR
I/O R(Z) I S(L) I/O K(Q) R(Z) I/O R(Z) O K(Q) R(Z)
P_PERR# P_REQ#
NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision 2.1 for a more complete definition.
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I960(R) Rx I/O Processor at 3.3 V
Table 7. PCI Signal Descriptions (Sheet 2 of 3) NAME P_RST# TYPE I A(L) DESCRIPTION1 PRIMARY RESET brings 80960Rx to a consistent state. When P_RST# is asserted: * PCI output signals are driven to a known consistent state. * PCI bus interface output signals are three-stated. * open drain signals such as P_SERR# are floated. * S_RST# asserts. P_RST# may be asynchronous to S_CLK when asserted or deasserted. Although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. P_SERR# I/O OD R(Z) I/O R(Z) P_TRDY# I/O R(Z) S_AD31:0 I/O R(0) I/O R(0) PRIMARY PCI BUS TARGET READY indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. SECONDARY PCI ADDRESS/DATA is the secondary multiplexed PCI address and data bus. A bus transaction consists of an address phase followed by one or more data phases. SECONDARY PCI BUS COMMAND and BYTE ENABLE signals are multiplexed on the same PCI signals. During an address phase, S_C/BE3:0# define the bus command. During a data phase, S_C/BE3:0# are used as byte enables. SECONDARY PCI BUS DEVICE SELECT is driven by a target agent that has successfully decoded the address. As an input, it indicates whether or not an agent has been selected. SECONDARY PCI BUS CYCLE FRAME is asserted to indicate the beginning and duration of an access on the Secondary PCI bus. SECONDARY PCI BUS GRANT0 is a grant signal sent to device 0 on the secondary PCI bus when the internal Secondary PCI Bus Arbiter is enabled. SECONDARY PCI BUS REQUEST is the request signal for the 80960Rx when the arbiter is disabled. SECONDARY PCI BUS GRANT are grant signals sent to devices 1-5 on the secondary PCI bus. SECONDARY PCI BUS INITIALIZATION DEVICE SELECT selects the 80960Rx during a Configuration Read or Write command on the secondary PCI bus. SECONDARY PCI BUS INITIATOR READY indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. PRIMARY PCI BUS SYSTEM ERROR reports address and data parity errors on the special cycle command, or any other system error where the result would be catastrophic. PRIMARY PCI BUS STOP indicates that the current target is requesting the master to stop the current transaction on the primary PCI bus.
P_STOP#
S_C/BE3:0#
S_DEVSEL#
I/O R(Z) I/O R(Z) O R(Z)
S_FRAME# S_GNT0#/ S_REQ#
S_GNT5:1# S_IDSEL
O R(Q) I S(L) I/O R(Z)
S_IRDY#
NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision 2.1 for a more complete definition. 16
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Table 7. PCI Signal Descriptions (Sheet 3 of 3) NAME S_LOCK# S_PAR S_PERR# S_REQ0#/ S_GNT# TYPE I/O R(Z) I/O R(0) I/O R(Z) I DESCRIPTION1 SECONDARY PCI BUS LOCK indicates the need to perform an atomic operation on the secondary PCI bus. SECONDARY PCI BUS PARITY. This signal ensures even parity across S_AD31:0 and S_C/BE3:0. All PCI devices must provide a parity signal. SECONDARY PCI BUS PARITY ERROR is used for reporting data parity errors during all PCI transactions except a special cycle. SECONDARY PCI BUS REQUEST0 is a request signal from device 0 on the secondary PCI bus when the internal Secondary PCI Bus Arbiter is enabled. SECONDARY PCI BUS GRANT is the grant signal for the 80960Rx when the arbiter is disabled. SECONDARY PCI BUS RESET is an output based on P_RST#. It brings PCI-specific registers, sequencers, and signals to a consistent state. When P_RST# is asserted, it causes S_RST# to assert, and: * PCI output signals are driven to a known consistent state. * PCI bus interface output signals are three-stated. * open drain signals such as S_SERR# are floated. S_RST# may be asynchronous to S_CLK when asserted or deasserted. S_SERR# I/O OD R(Z) I/O R(Z) I/O R(Z) I S(L) I S(L) SECONDARY PCI BUS SYSTEM ERROR reports address and data parity errors on the special cycle command, or any other system error where the result would be catastrophic. SECONDARY PCI BUS STOP indicates that the current target is requesting the master to stop the current transaction on the secondary PCI bus. SECONDARY PCI BUS TARGET READY indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. SECONDARY PCI BUS REQUEST 4:1 are request signals from devices 1-4 on the secondary PCI bus. SECONDARY PCI BUS REQUEST 5 is the request signal from device 5 on the secondary PCI bus. SECONDARY PCI BUS ARBITER ENABLE defines the power-up status of the internal secondary arbitration unit. A valid high at the deassertion of P_RST# enables the internal secondary arbiter. A valid low at the deassertion of P_RST# disables the internal secondary arbiter. NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification Revision 2.1 for a more complete definition.
S_RST#
O R(Q)
S_STOP#
S_TRDY#
S_REQ4:1# S_REQ5#/ S_ARB_EN
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Table 8. Memory Controller Signal Descriptions (Sheet 1 of 2) NAME CAS7:0# TYPE O R(1) H(Q) P(Q) DESCRIPTION COLUMN ADDRESS STROBE signals are used for DRAM accesses and are asserted when the MA11:0 signals contain a valid column address. CAS7:0# signals are asserted during refresh.
Non-Interleaved Operation: CAS0#,CAS4# = BE0# CAS1#,CAS5# = BE1# CAS2#,CAS6# = BE2# CAS3#,CAS7# = BE3# Interleaved Operation: CAS0# = BE0# CAS1# = BE1# CAS2# = BE2# CAS3# = BE3# CAS4# = BE0# CAS5# = BE1# CAS6# = BE2# CAS7# = BE3#
lane access lane access lane access lane access Even leaf lane access Even leaf lane access Even leaf lane access Even leaf lane access Odd leaf lane access Odd leaf lane access Odd leaf lane access Odd leaf lane access
CE1:0#
O R(1) H(Q) P(Q) O R(0) H(Q) P(Q) I/O R(X) H(Q) P(Q)
CHIP ENABLE signals indicate an access to one of the two SRAM/ FLASH/ ROM memory banks. CE0# and CE1# are never asserted at the same time. These signals are valid during the entire memory operation. CE0# is asserted for accesses to memory bank 0. CE1# is asserted for accesses to memory bank 1. DRAM ADDRESS LATCH ENABLE signals support external address demultiplexing of the MA11:0 address lines for interleaved DRAM systems. Use these to directly interface to `373' type latches. These signals are only valid for accesses to interleaved memory systems. DALE0 is asserted during a valid even leaf address. DALE1 is asserted during a valid odd leaf address. DATA PARITY carries the parity information for DRAM accesses. Each parity bit corresponds to a group of 8 data bus signals as follows: DP0 -- AD7:0 DP1 -- AD15:8 DP2 -- AD23:16 DP3 -- AD31:24
DALE1:0
DP3:0
The memory controller generates parity information for local bus writes during data cycles. During read data cycles, the memory controller checks parity and provides notification of parity errors on the clock following the data cycle. Parity checking and polarity are user-programmable. Parity generation and checking are valid only for data lines that have their associated enable bits asserted. DWE1:0# O R(1) H(Q) P(Q) O R(1) H(Q) P(Q) DRAM WRITE ENABLE signals distinguish between read and write accesses to DRAM. DWE1:0# lines are asserted for writes and deasserted for reads. CAS7:0# determine valid bytes lanes during the access. These two outputs are functionally equivalent for all DRAM accesses; these provide increased drive capability for heavily loaded systems. LEAF ENABLE signals control the data output enables of the memory system during an interleaved DRAM read access. Use these to directly interface to either DRAM or transceiver output enable signals. LEAF0# is asserted during an even leaf access. LEAF1# is asserted during an odd leaf access.
LEAF1:0#
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Table 8. Memory Controller Signal Descriptions (Sheet 2 of 2) NAME MA11:0 TYPE O R(X) H(Q) P(Q) DESCRIPTION MULTIPLEXED ADDRESS signals are multi-purpose depending on the device that is selected. For memory banks 0 and 1, these signals output address bits A13:2. These address bits are incremented for each data transfer of a burst access. For DRAM bank, these signals output the row/column multiplexed address bits 11:0. The relationship between the AD31:0 lines and the MA11:0 lines depends on the bank size, type and arrangement of the DRAM that is accessed. MWE3:0# O R(1) H(Q) P(Q) MEMORY WRITE ENABLE signals for write accesses to SRAM/FLASH devices. The MWE's rising edge strobes valid data into these devices. MWE0# is asserted for MWE1# is asserted for MWE2# is asserted for MWE3# is asserted for writes to the BE0# lane writes to the BE1# lane writes to the BE2# lane writes to the BE3# lane
RAS3:0#
O R(1) H(Q) P(Q)
ROW ADDRESS STROBE signals are used for DRAM accesses and are asserted when the MA11:0 signals contain a valid row address. RAS3:0# always deasserts after the last data transfer in a DRAM access.
Non-Interleaved Operation: RAS0# = Bank0 access RAS1# = Bank1 access RAS2# = Bank2 access RAS3# = Bank3 access Interleaved Operation: RAS0,2# = Even leaf RAS1,3# = Odd leaf
Table 9. DMA, APIC, I2C Units Signal Descriptions (Sheet 1 of 2) NAME DACK# TYPE O R(1) H(Q) P(Q) I S(L) I I/O OD R(Z) H(Q) P(Q) DESCRIPTION DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this signal to indicate (1) it can receive new data from an external device or (2) it has data to send to an external device. DMA DEMAND MODE REQUEST External devices use this signal to indicate (1) new data is ready for transfer to the DMA controller or (2) buffers are available to receive data from the DMA controller. APIC BUS CLOCK provides synchronous operation of the APIC bus. APIC DATA lines comprise the data portion of the APIC 3-wire bus.
DREQ#
PICCLK PICD1:0
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I960(R) Rx I/O Processor at 3.3 V
Table 9. DMA, APIC, I2C Units Signal Descriptions (Sheet 2 of 2) NAME SCL TYPE I/O OD R(Z) H(Q) P(Q) I/O OD R(Z) H(Q) P(Q) O R(1) H(Q) P(Q) DESCRIPTION I2C CLOCK provides synchronous I2C bus operation.
SDA
I2C DATA used for data transfer and arbitration on the I2C bus.
WAIT#
WAIT is an output that allows the DMA controller to insert wait states during DMA accesses to an external memory system.
Table 10. Clock Signal NAME S_CLK TYPE I DESCRIPTION SYNCHRONOUS PCI BUS CLOCK Provides the processor's fundamental time base. All input/output timings are relative to S_CLK.
Table 11. ICE Signal Descriptions NAME ICEADS# ICEBRK# ICEBUS7:0 ICECLK ICELOCK# ICEMSG# ICESEL# ICEVLD# MSGFRM# TYPE O I I/O O I I I O O DESCRIPTION ICE ADDRESS/DATA STATUS indicates a valid address and the start of a new bus access. ICEADS# is active for accesses to external microcode. ICE BREAK forces the processor to transition from emulation to interrogation mode. ICE BUS is a bidirectional 8-bit bus linking the processor and the emulator. Used in various modes. ICE CLOCK output signal to which all ICE bus signals are synchronized. ICE LOCK is sampled during 80960 core reset to protect ICE configuration. ICE MESSAGE signal used to acknowledge data from the processor to the emulator. Used only during interrogation mode. ICESEL enables or disables the ICE unit. ICE VALID indicates the processor is driving the ICEBUS with valid data. ICE MESSAGE FRAME indicates that trace messages are being issued to the ICEBUS. Used in emulation mode only.
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3.1.2
352-Lead HL-PBGA Package
Body Size 35 0.10 mm
I960(R)
i
Ball A1 Corner
GC80960RxZZ FFFFFFFF SS Q QQQQ M (c) `9x `9x
35 0.10 mm
1.63 mm 0.63 0.07 mm
Ball Footprint 31.75 mm Package Height Ball spacing is 1.27 mm 1.54 0.13 mm 0.91 0.06 mm
Ball width is 0.75 0.15 mm
NOTES: 1. All dimensions and tolerances conform to ANSI Y14.5M 1982. 2. All dimensions are in millimeters. 3. Tin/Lead mix: 63%/37%. 4. Pad plating method: Electrolytic. 5. Encapsulant size: 22.38 x 22.38 mm (max).
Figure 3. 352L HL-PBGA Package Diagram (Top and Side View)
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I960(R) Rx I/O Processor at 3.3 V
AF 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AF
AE
AD
AC AB
AA Y W V
U
T
R
PNM
L
K
J
HG
F
E
D
C
B
A
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AE AD AC AB AA Y W V U T R PNM L K J HG F E D C B A
Figure 4. 352L HL-PBGA Package Diagram (Bottom View)
22
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package -- Signal Name Order (Sheet 1 of 4) Signal AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADS# ALE BE0# BE1# BE2# BE3# BLAST# Ball # A18 B18 C17 A17 B17 C16 A16 B16 C15 A15 B15 C14 A14 B14 C13 A13 B13 C12 A12 B12 C11 A11 B11 C10 A10 B10 C9 A9 B9 C8 A8 B8 B21 C20 A22 B22 C21 A21 C23 Signal CAS0# CAS1# CAS2# CAS3# CAS4# CAS5# CAS6# CAS7# CE0# CE1# D/C#/RST_MODE# DACK# DALE0 DALE1 DEN# DP0 DP1 DP2 DP3 DREQ# DT/R# DWE0# DWE1# FAIL# HOLD HOLDA ICEADS# ICEBRK# ICEBUS0 ICEBUS1 ICEBUS2 ICEBUS3 ICEBUS4 ICEBUS5 ICEBUS6 ICEBUS7 ICECLK ICELOCK# ICEMSG# Ball # F1 F2 G3 G1 G2 H3 H1 H2 L3 L1 AF4 AD3 M1 M2 A23 C2 D3 D1 D2 AD2 B23 K1 K2 AD5 V1 V3 AC1 AA1 V2 W3 W1 W2 Y3 Y1 Y2 AA3 AB2 AB3 AA2 Signal ICESEL# ICEVLD# LEAF0 LEAF1 LOCK#/ONCE# LRDYRCV# LRST# MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MSGFRM# MWE0# MWE1# MWE2# MWE3# NC NC NC NC NMI# P_AD0 P_AD1 P_AD2 P_AD3 P_AD4 P_AD5 P_AD6 P_AD7 P_AD8 P_AD9 Ball # AC2 AB1 L2 M3 AD4 C19 AD6 C7 A7 B7 C6 B6 C5 A5 B5 C4 B4 C3 B3 AC3 J3 J1 J2 K3 A20 AE4 B20 C18 T3 AD24 AE23 AF23 AD23 AE22 AF22 AD22 AE21 AD21 AE20
ADVANCE INFORMATION
23
I960(R) Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package -- Signal Name Order (Sheet 2 of 4) Signal P_AD10 P_AD11 P_AD12 P_AD13 P_AD14 P_AD15 P_AD16 P_AD17 P_AD18 P_AD19 P_AD20 P_AD21 P_AD22 P_AD23 P_AD24 P_AD25 P_AD26 P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_C/BE0# P_C/BE1# P_C/BE2# P_C/BE3# P_DEVSEL# P_FRAME# P_GNT# P_IDSEL P_INTA# P_INTB# P_INTC# P_INTD# P_IRDY# P_LOCK# P_PAR P_PERR# P_REQ# Ball # AF20 AD20 AE19 AF19 AD19 AE18 AE14 AF14 AD14 AE13 AF13 AD13 AE12 AF12 AF11 AD11 AE10 AF10 AD10 AE9 AF9 AD9 AF21 AF18 AD15 AE11 AF16 AF15 AF8 AD12 AF6 AE6 AD7 AF7 AE15 AD17 AD18 AF17 AE8
Signal P_RST# P_SERR# P_STOP# P_TRDY# PICCLK PICD0 PICD1 RAS0# RAS1# RAS2# RAS3# RDYRCV# S_AD0 S_AD1 S_AD2 S_AD3 S_AD4 S_AD5 S_AD6 S_AD7 S_AD8 S_AD9 S_AD10 S_AD11 S_AD12 S_AD13 S_AD14 S_AD15 S_AD16 S_AD17 S_AD18 S_AD19 S_AD20 S_AD21 S_AD22 S_AD23 S_AD24 S_AD25 S_AD26 Ball # AE7 AE17 AE16 AD16 U3 T1 T2 E3 E1 E2 F3 B19 AE24 AD25 AC24 AC26 AC25 AB24 AB26 AB25 AA26 AA25 Y24 Y26 Y25 W24 W26 W25 R25 P24 P26 P25 N24 N26 N25 M24 L24 L26 L25 Signal S_AD27 S_AD28 S_AD29 S_AD30 S_AD31 S_C/BE0# S_C/BE1# S_C/BE2# S_C/BE3# S_CLK S_DEVSEL# S_FRAME# S_GNT0#/S_REQ# S_GNT1# S_GNT2# S_GNT3# S_GNT4# S_GNT5# S_IDSEL S_INTA#/XINT0# S_INTB#/XINT1# S_INTC#/XINT2# S_INTD#/XINT3# S_IRDY# S_LOCK# S_PAR S_PERR# S_REQ0#/S_GNT# S_REQ1# S_REQ2# S_REQ3# S_REQ4# S_REQ5#/S_ARB_EN S_RST# S_SERR# S_STOP# S_TRDY# SCL SDA Ball # K24 K26 K25 J24 J26 AA24 V24 R26 M25 F25 T24 R24 H26 G24 G25 F26 E26 D24 M26 N1 N2 P3 P1 T25 U26 V26 U24 H24 H25 G26 F24 E24 E25 J25 V25 U25 T26 U1 U2
24
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package -- Signal Name Order (Sheet 3 of 4)
Signal Ball # Signal VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC5 VCCPLL1 VCCPLL2 VCCPLL3 VSS VSS VSS VSS Ball # B25 B26 C1 C26 D5 D7 D9 D11 D13 D15 D17 D19 D21 E23 F4 G23 H4 J23 K4 L23 M4 N23 P4 R23 T4 U23 V4 W23 Y4 A3 A19 A6 A4 AA4 AB23 AC4 AC5 Signal V SS VSS VSS V SS V SS V SS V SS V SS V SS V SS V SS V SS V SS VSS VSS VSS VSS VSS VSS VSS VSS VSS V SS V SS VSS V SS VSS V SS V SS V SS V SS V SS V SS V SS V SS V SS W/R# Ball # AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D23 E4 F23 G4 H23 J4 K23 L4 M23 N4 P23 R4 T23 U4 V23 W4 Y23 C22
STEST TCK TDI TDO TMS TRST# VCC
V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC V CC VCC /VSS (1) V CC V CC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC V CC
AE3 B24 D26 D25 C24 C25
A1 A2 A24 A25 A26 AA23 AB4 AC6 AC8 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AD1 AD8 AD26 AE1 AE2 AE25 AE26 AF1 AF2 AF3 AF24 AF25 AF26 B1 B2
NOTES: 1. Ball AD8 must be tied to either VCC or VSS.
ADVANCE INFORMATION
25
I960(R) Rx I/O Processor at 3.3 V
Table 12. 352-Lead HL-PBGA Package -- Signal Name Order (Sheet 4 of 4) Signal WAIT# WIDTH/HLTD0 WIDTH/HLTD1/RETRY Ball # N3 AF5 AE5 Signal XINT4# XINT5# XINT6# Ball # P2 R3 R1 Signal XINT7# Ball # R2
26
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout -- Ballpad Number Order (Sheet 1 of 4) Ball # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 B6 B7 B8 B9 Signal V CC V CC VCC5 VCCPLL3 MA6 VCCPLL2 MA1 AD30 AD27 AD24 AD21 AD18 AD15 AD12 AD9 AD6 AD3 AD0 VCCPLL1 NC BE3# BE0# DEN# VCC VCC VCC V CC V CC MA11 MA9 MA7 MA4 MA2 AD31 AD28 Ball # B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 Signal AD25 AD22 AD19 AD16 AD13 AD10 AD7 AD4 AD1 RDYRCV# NC ADS# BE1# DT/R# TCK VCC VCC VCC DP0 MA10 MA8 MA5 MA3 MA0 AD29 AD26 AD23 AD20 AD17 AD14 AD11 AD8 AD5 AD2 NC Ball # C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 Signal LRDYRCV# ALE BE2# W/R# BLAST# TMS TRST# VCC DP2 DP3 DP1 VSS VCC VSS VCC VSS VCC V SS VCC V SS VCC V SS VCC V SS VCC V SS VCC V SS VCC V SS V SS S_GNT5# TDO TDI RAS1#
ADVANCE INFORMATION
27
I960(R) Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout -- Ballpad Number Order (Sheet 2 of 4)
Ball # Signal Ball # J23 J24 J25 J26 K1 K2 K3 K4 K23 K24 K25 K26 L1 L2 L3 L4 L23 L24 L25 L26 M1 M2 M3 M4 M23 M24 M25 M26 N1 N2 N3 N4 N23 N24 N25 Signal VCC S_AD30 S_RST# S_AD31 DWE0# DWE1# MWE3# VCC VSS S_AD27 S_AD29 S_AD28 CE1# LEAF0# CE0# VSS VCC S_AD24 S_AD26 S_AD25 DALE0 DALE1 LEAF1# VCC VSS S_AD23 S_C/BE3# S_IDSEL S_INTA#/XINT0# S_INTB#/XINT1# WAIT# VSS VCC S_AD20 S_AD22 Ball # N26 P1 P2 P3 P4 P23 P24 P25 P26 R1 R2 R3 R4 R23 R24 R25 R26 T1 T2 T3 T4 T23 T24 T25 T26 U1 U2 U3 U4 U23 U24 U25 U26 V1 V2 Signal S_AD21 S_INTD#/XINT3# XINT4# S_INTC#/XINT2# VCC VSS S_AD17 S_AD19 S_AD18 XINT6# XINT7# XINT5# VSS VCC S_FRAME# S_AD16 S_C/BE2# PICD0 PICD1 NMI# V CC VSS S_DEVSEL# S_IRDY# S_TRDY# SCL SDA PICCLK VSS VCC S_PERR# S_STOP# S_LOCK# HOLD ICEBUS0
E2 E3 E4
E23 E24 E25 E26 F1 F2 F3 F4 F23 F24 F25 F26 G1 G2 G3 G4 G23 G24 G25 G26 H1 H2 H3 H4 H23 H24 H25 H26 J1 J2 J3 J4
RAS2# RAS0# VSS
VCC S_REQ4# S_REQ5#/S_ARB_EN S_GNT4# CAS0# CAS1# RAS3# VCC VSS S_REQ3# S_CLK S_GNT3# CAS3# CAS4# CAS2# VSS VCC S_GNT1# S_GNT2# S_REQ2# CAS6# CAS7# CAS5# VCC V SS S_REQ0#/S_GNT# S_REQ1# S_GNT0#/S_REQ# MWE1# MWE2# MWE0# VSS
28
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout -- Ballpad Number Order (Sheet 3 of 4)
Ball # Signal Ball # AB4 AB23 AB24 AB25 AB26 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 Signal VCC VSS S_AD5 S_AD7 S_AD6 ICEADS# ICESEL# MSGFRM# VSS VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS S_AD2 S_AD4 S_AD3 VCC DREQ# Ball # AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 Signal DACK# LOCK#/ONCE# FAIL# LRST# P_INTC# VCC/VSS (1) P_AD31 P_AD28 P_AD25 P_IDSEL P_AD21 P_AD18 P_C/BE2# P_TRDY# P_LOCK# P_PAR P_AD14 P_AD11 P_AD8 P_AD6 P_AD3 P_AD0 S_AD1 VCC VCC VCC STEST NC WIDTH/HLTD1/RETRY P_INTB# P_RST# P_REQ# P_AD29
V3 V4
V23 V24 V25 V26 W1 W2 W3 W4 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA23 AA24 AA25 AA26 AB1 AB2 AB3
HOLDA VCC
VSS S_C/BE1# S_SERR# S_PAR ICEBUS2 ICEBUS3 ICEBUS1 VSS V CC S_AD13 S_AD15 S_AD14 ICEBUS5 ICEBUS6 ICEBUS4 V CC VSS S_AD10 S_AD12 S_AD11 ICEBRK# ICEMSG# ICEBUS7 VSS V CC S_C/BE0# S_AD9 S_AD8 ICEVLD# ICECLK ICELOCK#
NOTES: 1. Ball AD8 must be tied to either VCC or VSS.
ADVANCE INFORMATION
29
I960(R) Rx I/O Processor at 3.3 V
Table 13. 352-Lead HL-PBGA Pinout -- Ballpad Number Order (Sheet 4 of 4) Ball # AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 Signal P_AD26 P_C/BE3# P_AD22 P_AD19 P_AD16 P_IRDY# P_STOP# P_SERR# P_AD15 P_AD12 P_AD9 P_AD7 P_AD4 P_AD1 S_AD0
Ball # AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 Signal VCC VCC VCC VCC VCC D/C#/RST_MODE# WIDTH/HLTD0 P_INTA# P_INTD# P_GNT# P_AD30 P_AD27 P_AD24 P_AD23 P_AD20 Ball # AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Signal P_AD17 P_FRAME# P_DEVSEL# P_PERR# P_C/BE1# P_AD13 P_AD10 P_C/BE0# P_AD5 P_AD2 VCC VCC VCC
30
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
3.2
Package Thermal Specifications
The device is specified for operation when TC (case temperature) is within the range of 0 C to 95 C. Case temperature may be measured in any environment to determine whether the processor is within specified operating range. Measure the case temperature at the center of the top surface, opposite the ballpad. 3.2.1 Thermal Specifications
* Attach the thermocouple bead or junction at a 90 angle by an adhesive bond (such as thermal epoxy or heat-tolerant tape) to the package top surface as shown in Figure 5. When a heat sink is attached, drill a hole through the heat sink to allow contact with the package above the center of the die. The hole diameter should be no larger than 3.8 mm as shown in Figure 6.
Thermocouple Wire Thermocouple Bead Epoxy Fillet
This section defines the terms used for thermal analysis. 3.2.1.1 Ambient Temperature Ambient temperature, TA, is the temperature of the ambient air surrounding the package. In a system environment, ambient temperature is the temperature of the air upstream from the package. 3.2.1.2 Case Temperature To ensure functionality and reliability, the device is specified for proper operation when the case temperature, TC, is within the specified range in Table 16, Operating Conditions (pg. 34). When measuring case temperature, attention to detail is required to ensure accuracy. If a thermocouple is used, calibrate it before taking measurements. Errors may result when the measured surface temperature is affected by the surrounding ambient air temperature. Such errors may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. To minimize measurement errors: * Use a 35 gauge K-type thermocouple or equivalent. * Attach the thermocouple bead or junction to the package top surface at a location corresponding to the center of the die (Figure 5). The center of the die gives a more accurate measurement and less variation as the boundary condition changes.
Figure 5. Thermocouple Attachment No Heat Sink
Thermocouple 3.8 mm Diameter Hole Heat Sink
Figure 6. Thermocouple Attachment With Heat Sink 3.2.1.3 Thermal Resistance The thermal resistance value for the case-toambient, CA, is used as a measure of the cooling solution's thermal performance.
ADVANCE INFORMATION
31
I960(R) Rx I/O Processor at 3.3 V
3.2.2
Thermal Analysis
This thermal analysis is based on the following assumptions: * Power dissipation is a constant 5 W. * Maximum case temperature is 95 C. Table 14 lists the case-to-ambient thermal resistances of the 80960RP for different air flow rates with and without a heat sink. To calculate TA, the maximum ambient temperature to conform to a particular case temperature: TA = TC - P (CA)
Compute P by multiplying ICC and VCC. Valuesfor JC and CA are given in Table 14. Junction temperature (TJ ) is commonly used in reliability calculations. TJ can be calculated from JC (thermal resistance from junction to case) using the following equation: TJ = TC + P (JC ) Similarly, when TA is known, the corresponding case temperature (TC) can be calculated as follows: TC = TA + P (CA) The JA (Junction to Ambient) for this package is currently estimated at 9.74 C/Watt with no airflow. JA = JC + CA
Table 14. 352-Lead HL-PBGA Package Thermal Characteristics Thermal Resistance -- C/Watt Airflow -- ft./min (m/sec) Parameter JC (Junction-to-Case) CA (Case-to-Ambient) Without Heatsink CA (Case-to-Ambient) With Heatsink2 0 (0) 0.60 9.14 50 (0.25) 0.60 7.64 100 (0.50) 0.60 6.58 200 (1.01) 0.60 6.11 300 (1.52) 0.60 5.79 400 (2.03) 0.60 5.61 600 (3.04) 0.60 5.49 800 (4.06) 0.60 5.47
7.31
6.00
JA
5.21
4.80
4.52
4.37
4.26
4.23
JC
CA
NOTES: 1. This table applies to a HL-PBGA device soldered directly onto a board. 2. See Table 15 for heatsink information.
32
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
3.3
Sources for Heatsinks and Accessories
The following is a list of suggested sources for heatsinks and accessories. This is neither an endorsement nor a warranty of the performance of any of the listed products and/or companies. Table 15. Heatsink Information Manufacturer Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75234-8993 Tel: (214) 243-4321 FAX: (214) 241-4656 Parker Chromerics 77 Dragon Court Woburn, MA 01888 Tel: (617) 935-4850 FAX: (617) 933-4318 AAVID Thermal Technologies, Inc. One Kool Path P.O. Box 400 Laconia, N.H. 13247-0400 Tel: (603) 528-3400 FAX: (603) 527-2129 Part No. Heatsink: 2338B BGA Clip: 20812-2 Heatsink Dimensions (mm) 32 X 34 X 12.6 Product Description Thermalloy Heatsink; use with BGA Clip and Parker Chromerics Thermflow tape Thermflow tape; use with Thermalloy BGA Clip
T705
NA
Heatsink: 364424B00032
40.5 X 40 X 11
AAVID Heatsink; use with pre-applied thermal adhesive tape (Ther-A-Grip)
ADVANCE INFORMATION
33
I960(R) Rx I/O Processor at 3.3 V
4.0 4.1
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings
Parameter Maximum Rating
-55 C to + 125 C
NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Storage Temperature Case Temperature Under Bias Supply Voltage wrt. VSS Voltage on Any Ball wrt. VSS
0 C to + 95 C
-0.5 V to + 4.6 V -0.5 V to VCC + 0.5 V
Supply Voltage wrt. VSS on VCC5 -0.5 V to + 6.5 V
Table 16. Operating Conditions Symbol VCC VCC5 FS_CLK TC Parameter Supply Voltage Input Protection Bias Input Clock Frequency Case Temperature Under Bias GC80960Rx (352 HL-PBGA) Min 3.0 3.0 16 0 Max 3.6 5.25 33.33 95 Units V V MHz C Notes
4.2
VCC5 Pin Requirements (V DIFF)
In mixed voltage systems that drive 80960Rx processor inputs in excess of 3.3 V, the VCC5 pin must be connected to the system's 5 V supply. To limit current flow into the VCC5 pin, there is a limit to the voltage differential between the VCC5 pin and the other VCC pins. The voltage differential between the 80960Rx VCC5 pin and its 3.3 V VCC pins should never exceed 2.25 V. This limit applies to power-up, power-down, and steady-state operation. Table 17 outlines this requirement. Meeting this requirement ensures proper operation and guarantees that the current draw into the VCC5 pin does not exceed the ICC5 specification. If the voltage difference requirements cannot be met due to system design limitations, an alternate solution may be employed. As shown in Figure 7, a minimum of 100 series resistor may be used to
limit the current into the VCC5 pin. This resistor ensures that current drawn by the VCC5 pin does not exceed the maximum rating for this pin.
+5 V (0.25 V) 100 (5%, 0.5 W)
VCC5 Pin
Figure 7. VCC5 Current-Limiting Resistor This resistor is not necessary in systems that can guarantee the VDIFF specification. In 3.3 V-only systems and systems that drive 80960Rx pins from 3.3 V logic, connect the VCC5 pin directly to the 3.3 V VCC plane.
Table 17. VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V) Symbol VDIFF Parameter VCC5-VCC Difference Min Max 2.25 Units V Notes VCC5 input should not exceed VCC by more than 2.25 V during power-up and power-down, or during steady-state operation.
34
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
4.3
Targeted DC Specifications
Table 18. DC Characteristics
Symbol VIL VIH1 VIH2 VOL1 VOH1 VOL2 VOH2 VOL3 VOH3 VOL4 VOH4 VOL5 CIN COUT CCLK CIDSEL LPIN
Parameter Input Low Voltage Input High Voltage for all signals except SCLK Input High Voltage for SCLK Output Low Voltage Processor signals Output High Voltage Processor signals Output Low Voltage PCI signals Output High Voltage PCI signals Output Low Voltage Memory Controller Normal drive Output High Voltage Memory Controller Normal drive Output Low Voltage Memory Controller High Drive Output High Voltage Memory Controller High Drive Output Low Voltage APIC Data Lines Input Capacitance - HL-PBGA I/O or Output Capacitance - HL-PBGA S_CLK Capacitance - HL-PBGA IDSEL Ball Capacitance Ball Inductance
Min -0.5 2.0 2.1
Max 0.8
VCC + 0.5 VCC + 0.5
Units V V V V V (1) (1) (1)
Notes
0.45 2.4 VCC - 0.5 0.55 2.4 0.45 2.4 0.45 2.4 0.45 10 10 5 12 8 20
IOL = 6 mA (3) IOH = -2 mA (3) IOH = -200 A (3) IOL = 6 mA (1) IOH = -2 mA (1) IOL = 6 mA (4) IOH = -2 mA (4) IOL = 7 mA IOH = -2 mA IOL = 10 mA FS_CLK = TF Min (1, 2) FS_CLK = TF Min (1, 2) FS_CLK = TF Min (1, 2) (1) (1)
V V V V V V V pF pF pF pF nH
NOTES: 1. As required by the PCI Local Bus Specification Revision 2.1. 2. Not tested. 3. Processor signals include AD31:0, ALE, ADS#, BE3:0#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE#, W/R#, DT/R#, DEN#, BLAST#, LRDYRCV#, LOCK#/ONCE#, HOLD, FAIL#, TDO, DACK#, WAIT#, SDA, SCL. 4. Memory Controller signals include MA11:0, DP3:0, RAS3:0#, CAS7:0#, MWE3:0#, DWE1:0#, DALE1:0, CE1:0#, LEAF1:0#. 5. Memory Controller signals capable of high drive are MA11:0, CAS7:0#, RAS3:0#, DWE1:0#.
ADVANCE INFORMATION
35
I960(R) Rx I/O Processor at 3.3 V
Table 19. ICC Characteristics Symbol ILI1 Parameter Input Leakage Current for each signal except PCI Bus Signals, LOCK#/ONCE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, BLAST#, D/C#/RST_MODE#, DEN#,TMS, TRST#, TDI Input Leakage Current for LOCK#/ONCE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, BLAST#, D/C#/RST_MODE#, DEN#, TMS, TRST#, TDI Input Leakage Current for PCI Bus Signals Output Leakage Current -140 Typ Max 80 Units A Notes 0 VIN VCC
ILI2
-250
A
VIN = 0.45 V (1)
ILI3 ILO
5 5 1.00 1.30
A A A
0 VIN VCC 0.4 VOUT VCC (1,2)
ICC Active Power Supply Current 80960RP 33/3.3 (Power Supply) 80960RD 66/3.3 ICC Active (Thermal) Thermal Current 80960RP 33/3.3 80960RD 66/3.3 0.75 0.95
A
(1,3)
Reset Mode ICC Active 80960RP 33/3.3 (Power Modes) 80960RD 66/3.3 ONCE Mode 80960RP 33/3.3 80960RD 66/3.3
A 0.65 0.80 0.02 0.02
(4) (4)
NOTES: 1. Measured with device operating and outputs loaded to the test condition in Figure 8. 2. ICC Active (Power Supply) value is provided for selecting your system's power supply. It is measured using one of the worst case instruction mixes with VCC = 3.6 V and ambient temperature = 55 C. This parameter is characterized but not tested. 3. ICC Active (Thermal) value is provided for your system's thermal management. Typical ICC is measured with VCC = 3.3 V and ambient temperature = 55 C. This parameter is characterized but not tested. 4. ICC Active (Power modes) refers to the ICC values that are tested when the device is in Reset mode or ONCE mode with VCC = 3.6 V and ambient temperature = 55 C.
36
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
4.4
Targeted AC Specifications
Table 20. Input Clock Timings
Symbol TF TC TCS TCH TCL TCR TCF
Parameter S_CLK Frequency S_CLK Period S_CLK Period Stability S_CLK High Time S_CLK Low Time S_CLK Rise Time S_CLK Fall Time
Min 16 30
Max 33.33 62.5 250
Units MHz ns ps ns ns (1)
Notes
Adjacent Clocks (2,3) Measured at 1.5 V (2,3) Measured at 1.5 V (2,3) 0.4 V to 2.4 V (2,3) 2.4 V to 0.4 V (2,3)
12 12 4 4
V/ns V/ns
NOTES: 1. See Figure 9. 2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the S_CLK frequency. 3. Not tested.
Table 21. Synchronous Output Timings Symbol TOV1 TOV2 TOV3 TOV4 TOV5 TOF Parameter Output Valid Delay - All Local Bus Signals Except ALE Inactive and DT/R# Output Valid Delay, DT/R# Output Valid Delay - PCI Signals Except P_REQ#, S_GNT0#/S_REQ#, and S_GNT5:1# Output Valid Delay P_REQ#, S_GNT0#/S_REQ#, and S_GNT5:1# Output Valid Delay - DP3:0 Output Float Delay Min 3 Max 15.5 Units ns ns ns ns ns ns Notes (1,2,5) (2,5) (2,5) (2,5) (2,5) (3,4,5)
0.5 TC +3 0.5 TC +15 2 2 3 3 11 12 19 13
NOTES: 1. Inactive ALE refers to the falling edge of ALE. For inactive ALE timings, see Table 23, Relative Output Timings (pg. 39). 2. See Figure 10, TOV Output Delay Waveform (pg. 45). 3. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is designed to be no longer than the valid delay. 4. See Figure 11, TOF Output Float Waveform (pg. 45). 5. Outputs precharged to VCC5 maximium.
ADVANCE INFORMATION
37
I960(R) Rx I/O Processor at 3.3 V
Table 22. Synchronous Input Timings Sym TIS1 TIS1A TIS1B TIH1 TIS2 TIH2 TIS3 TIH3 TIS4 TIH4 TIS5 TIH5 TIS6 TIH6 TIS7 TIS8 TIS9 TIH9 Parameter Input Setup to S_CLK -- NMI#, XINT7:4#, S_INT[A:D]#/XINT3:0#, DP3:0# Input Setup to S_CLK -- for all accesses except Expansion ROM Accesses -- AD31:0 only Input Setup to S_CLK during Expansion ROM Accesses -- AD31:0 only Input Hold from S_CLK -- AD31:0, NMI#, XINT7:4#, S_INT[A:D]#/XINT3:0#, DP3:0# Input Setup to S_CLK -- RDYRCV# and HOLD Input Hold from S_CLK -- RDYRCV# and HOLD Input Setup to S_CLK -- LOCK#/ONCE#, STEST Input Hold from S_CLK -- LOCK#/ONCE#, STEST Input Setup to S_CLK -- DREQ# Input Hold from S_CLK -- DREQ# Input Setup to S_CLK -- PCI Signals Except P_GNT#, S_REQ0#/S_GNT#, and S_REQ5:1# Input Hold from S_CLK -- PCI Signals Input Setup to S_CLK -- P_RST# Input Hold to S_CLK -- P_RST# Input Setup to S_CLK -- P_GNT# Input Setup to S_CLK -- S_REQ0#/S_GNT# and S_REQ5:1# Input Setup to P_RST# -- WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE# Input Hold from P_RST# -- WIDTH/HLTD0, WIDTH/HLTD1/RETRY, D/C#/RST_MODE# Min Max 6 6 8 2 10 2 7 3 12 7 7 0 6 2 10 12 7 3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Notes (1,2) (1,2) (1,2) (1,2,4) (2) (2) (1,2) (1,2) (2) (2) (2) (2,4) (2,3) (2,3) (2) (2) (1,2,4) (1,2,4)
NOTES: 1. Setup and hold times must be met for proper processor operation. NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. For asynchronous operation, NMI#, XINT7:4#, and S_INT[A:D]#/XINT3:0# must be asserted for a minimum of two S_CLK periods to guarantee recognition. 2. See Figure 12, TIS and TIH Input Setup and Hold Waveform (pg. 46). 3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. 4. Guaranteed by design. May not be 100% tested.
38
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
4.4.1
Relative Output Timings Table 23. Relative Output Timings
Symbol TLXL TLXA TDXD ALE Width
Parameter
Min 0.5TC-3 0.5TC-3 0.5TC-3
Max
Units ns ns ns (1,2,4)
Notes
Address Hold from ALE Inactive DT/R# Valid to DEN# Active
Equal Loading (1,2,4) Equal Loading (1,3,4)
NOTES: 1. Guaranteed by design. May not be 100% tested. 2. See Figure 13. 3. See Figure 14. 4. Outputs precharged to VCC5 maximium.
4.4.2
Memory Controller Relative Output Timings Table 24. Fast Page Mode Non-interleaved DRAM Output Timings
Symbol TOV6 TOV7 TOV8 TOV9 TOV10 TOV11
Description RAS3:0# Rising and Falling edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay CAS7:0# Falling Edge Output Valid Delay MA11:0 Output Valid Delay-Row Address MA11:0 Output Valid Delay-Column Address DWE1:0# Rising and Falling edge Output Valid Delay
Min 2 2 0.5Tc+2 0.5Tc+2 2 2
Max 9 8 0.5Tc+8 0.5Tc+10 10 11
Units ns ns ns ns ns ns
Notes 2 2 1,2 1,2 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS.
ADVANCE INFORMATION
39
I960(R) Rx I/O Processor at 3.3 V
Table 25. Fast Page Mode Interleaved DRAM Output Timings Symbol TOV12 TOV13 TOV14 TOV15 TOV16 TOV17 TOV18 TOV19 TOV20 TOV21 Description RAS3:0# Rising and Falling edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay CAS7:0# Falling Edge Output Valid Delay MA11:0 Output Valid Delay-Row Address MA11:0 Output Valid Delay-Column Address DWE1:0# Rising and Falling Edge Output Valid Delay DALE1:0 Initial Falling Edge Output Valid Delay DALE1:0 Burst Falling Edge Output Valid Delay DALE1:0 Rising Edge Output Valid Delay LEAF1:0# Rising and Falling Edge Output Valid Delay Min 2 2 0.5Tc+2 0.5Tc+2 2 2 2 0.5Tc+2 2 2 Max 9 8 0.5Tc+8 0.5Tc+10 10 11 10 0.5Tc+10 10 10 Units ns ns ns ns ns ns ns ns ns ns Notes 2 2 1,2 1,2 2 2 2 1,2 2 2
NOTE: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS.
Table 26. EDO DRAM Output Timings Symbol TOV22 TOV23 TOV24 TOV25 TOV26 TOV27 TOV28 TOV29 TOV30 Description RAS3:0# Rising and Falling Edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay Read Cycles CAS7:0# Falling Edge Output Valid Delay Read Cycles CAS7:0# Rising Edge Output Valid Delay Write Cycles CAS7:0# Falling Edge Output Valid Delay Write Cycles MA11:0 Output Valid Delay - Row Address Min 2 0.5Tc+2 2 2 0.5Tc+2 0.5Tc+2 Max 9 0.5Tc+8 8 8 0.5Tc+8 0.5Tc+10 0.5Tc+10 10 11 Units Notes ns ns ns ns ns ns ns ns ns 2 1,2 2 2 1,2 1,2 1,2 2 2
MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc+2 MA11:0 Output Valid Delay - Column Address Write Cycles DWE1:0# Rising and Falling Edge Output Valid Delay 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS.
40
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 27. BEDO DRAM Output Timings Symbol TOV31 TOV32 TOV33 TOV34 TOV35 TOV36 TOV37 TOV38 TOV39 Description RAS3:0# Rising and Falling Edge Output Valid Delay CAS7:0# Rising Edge Output Valid Delay - Read Cycles CAS7:0# Falling Edge Output Valid Delay - Read Cycles CAS7:0# Rising Edge Output Valid Delay - Write Cycles CAS7:0# Falling Edge Output Valid Delay - Write Cycles MA11:0 Output Valid Delay - Row Address Min 2 0.5Tc+2 2 2 0.5Tc+2 Max 9 0.5Tc+8 8 8 0.5Tc+8 Units ns ns ns ns ns ns ns ns ns Notes 2 1,2 2 2 1,2 1,2 1,2 2 2
0.5Tc +2 0.5Tc+10
MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc +2 0.5Tc+10 MA11:0 Output Valid Delay - Column Address Write Cycles DWE1:0# Rising and Falling Edge Output Valid Delay 2 2 10 11
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS.
Table 28. SRAM/ROM Output Timings Symbol TOV40 TOV41 TOV42 TOV43 TOV44 Description CE1:0# Rising and Falling Edge Output Valid Delay MWE3:0# Rising Edge Output Valid Delay MWE3:0# Falling Edge Output Valid Delay MA11:0 Output Valid Delay - Initial Address MA11:0 Output Valid Delay - Burst Address Min 2 1 0.5Tc +1 0.5Tc +2 2 Max 8 9 0.5Tc +9 0.5Tc +10 10 Units ns ns ns ns ns Notes 2 2 1,2 2 2
NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period. For testing purposes, the signal is specified relative to the rising edge of S_CLK with the 0.5Tc period offset. 2. Output switching between VCC3 maximium and VSS.
ADVANCE INFORMATION
41
I960(R) Rx I/O Processor at 3.3 V
4.4.3
Boundary Scan Test Signal Timings Table 29. Boundary Scan Test Signal Timings
Symbol TBSF TBSCH TBSCL TBSCR TBSCF TBSIS1 TBSIH1 TBSOV1 TBSOF1 TBSOV2 TBSOF2 TBSIS2 TBSIH2
Parameter TCK Frequency TCK High Time TCK Low Time TCK Rise Time TCK Fall Time Input Setup to TCK -- TDI, TMS Input Hold from TCK -- TDI, TMS TDO Valid Delay TDO Float Delay All Outputs (Non-Test) Valid Delay All Outputs (Non-Test) Float Delay Input Setup to TCK -- All Inputs (Non-Test) Input Hold from TCK -- All Inputs (Non-Test)
Min 0 15 15
Max 0.5TF
Units MHz ns ns
Notes
Measured at 1.5 V (1) Measured at 1.5 V (1) 0.8 V to 2.0 V (1) 2.0 V to 0.8 V (1)
5 5 4 6 3 3 3 3 4 6 30 30 30 30
ns ns ns ns ns ns ns ns ns ns
Relative to falling edge of TCK (2) Relative to falling edge of TCK (2) Relative to falling edge of TCK (2) Relative to falling edge of TCK (2)
NOTES: 1. Not tested. 2. Outputs precharged to VCC5 maximium.
4.4.4
APIC Bus Interface Signal Timings Table 30. APIC Bus Interface Signal Timings (Sheet 1 of 2)
Symbol TAPF TAPC TAPCH TAPCL TAPCR TAPCF
NOTES: 1. Not tested.
Parameter PICCLK Frequency PICCLK Period PICCLK High Time PICCLK Low Time PICCLK Rise Time PICCLK Fall Time
Min 2 60 9 9 1 1
Max 16.66 500
Units MHz ns ns ns
Notes
5 5
ns ns
(1) (1)
42
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
Table 30. APIC Bus Interface Signal Timings (Sheet 2 of 2) Symbol TAPIS1 TAPIH1 TAPOF TAPOVI
NOTES: 1. Not tested.
Parameter Input Setup to PICCLK -- PICD1:0 Input Hold from PICCLK -- PICD1:0 Output Float Delay from PICCLK -- PICD1:0 Output Valid Delay from PICCLK -- PICD1:0 (High to Low)
Min 3 2.5 4 4
Max
Units ns ns
Notes
16 22
ns ns
(1)
4.4.5
I2C Interface Signal Timings Table 31. I2C Interface Signal Timings
Symbol FSCL TBUF THDSTA TLOW THIGH TSUSTA THDDAT TSUDAT TR TF TSUSTO
Parameter SCL Clock Frequency Bus Free Time Between STOP and START Condition Hold Time (repeated) START Condition SCL Clock Low Time SCL Clock High Time Setup Time for a Repeated START Condition Data Hold Time Data Setup Time SCL and SDA Rise Time SCL and SDA Fall Time Setup Time for STOP Condition
Std. Mode Min 0 4.7 4 4.7 4 4.7 0 250 1000 300 4 Max 100
Fast Mode Min 0 1.3 0.6 1.3 0.6 0.6 0 100 20+0.1Cb 20+0.1Cb 0.6 300 300 0.9 Max 400
Units KHz s s s s s s ns ns ns s
Notes
(1) (1,3) (1,2) (1,2) (1) (1) (1) (1,4) (1,4) (1)
NOTES: 1. See Figure 15. 2. Not tested. 3. After this period, the first clock pulse is generated. 4. Cb = the total capacitance of one bus line, in pF.
ADVANCE INFORMATION
43
I960(R) Rx I/O Processor at 3.3 V
4.5
AC Test Conditions
The AC Specifications in Section 4.4, Targeted AC Specifications (pg. 37) are tested with the 50 pF load indicated in Figure 8.
Output Ball CL = 50 pF for all signals CL
Figure 8. AC Test Load
4.6
AC Timing Waveforms
TCR
TCF
2.0V
1.5V
0.8V
TCH
TCL
TC
Figure 9. S_CLK, TCLK Waveform
44
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
S_CLK
1.5V
1.5V
TOVX Max
TOVX Min
1.5V
Valid
1.5V
Figure 10. TOV Output Delay Waveform
S_CLK
1.5V
1.5V
TOF
Figure 11. TOF Output Float Waveform
ADVANCE INFORMATION
45
I960(R) Rx I/O Processor at 3.3 V
S_CLK
1.5V
1.5V
1.5V
TIHX TISX
1.5V
Valid
Figure 12. TIS and TIH Input Setup and Hold Waveform
TA
TW/TD
S_CLK
1.5V TLXL
1.5V
1.5V
ALE 1.5V
Valid
1.5V
TLXA AD31:0 1.5V 1.5V
Valid
Figure 13. TLXL and TLXA Relative Timings Waveform
46
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
TA
TW/TD
S_CLK
1.5V TOVX
1.5V
1.5V
DT/R#
Valid
TDXD
DEN#
TOVX
Figure 14. DT/R# and DEN# Timings Waveform
SDA
TBUF TLOW
TR
TF
THDSTA
TSP
SCL
THDSTA Stop Start THDDAT THIGH TSUSTO TSUDAT TSUSTA Repeated Start Stop
Figure 15. I2C Interface Signal Timings
ADVANCE INFORMATION
47
I960(R) Rx I/O Processor at 3.3 V
4.7
Memory Controller Output Timing Waveforms
TA S_CLK Tw Tw Td Tw Td Tw Td Tw Td Tr
AD31:0
ADDR
DATA In
DATA In
DATA In
DATA In
MA11:0
ROW
COL
COL
COL
COL
ALE
ADS#
W/R#
BLAST#
DT/R#
DEN#
DWE0#
RAS0#
CAS3:0#
LRDYRCV# RDYRCV#
Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus
48
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
Tw
Tw
Td
Tw
Td
Tw
Td
Tw
Td
Tr
AD31:0
ADDR
DATA OUT
DATA OUT
DATA OUT
DATA OUT
MA11:0
ROW
COL
COL
COL
COL
ALE
ADS#
BE3:0#
W/R#
BLAST#
DT/R#
MWE0#
DWE0#
RAS0#
CAS3:0# LRDYRCV# RDYRCV#
Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus
ADVANCE INFORMATION
49
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TW
TW
TD
TD
TD
TD
TR
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
RAS[n]# RAS[n+1#] COL
MA[11:0]
ROW
COL
DALE[0]#
CAS[3:0]#
LEAF[0]#
DALE[1]#
CAS[7:4]#
LEAF[1]#
DWE[1:0]#
Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States
50
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TW
TD
TD
TD
TD
TR
TR
AD[31:0]
ADDR
DATA OUT
DATA OUT
DATA OUT
DATA OUT
RAS[n]# RAS[n+1]#
MA[11:0]
ROW
COL
COL
DALE[0]#
CAS[3:0]#
LEAF[0]#
DALE[1]#
CAS[7:4]#
LEAF[1]#
DWE[1:0]#
Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States
ADVANCE INFORMATION
51
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TW
TW
TD
TD
TD
TD
TR
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
CAS#
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
Figure 20. EDO DRAM, Read Cycle
TA S_CLK
TW
TD
TD
TD
TD
TR
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
CAS#
AD[31:0]
ADDR
D OUT
D OUT
D OUT
D OUT
Figure 21. EDO DRAM, Write Cycle
52
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
A S_CLK
3
2
1
D
D
D
D
Tr
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
COL
CAS#
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
Figure 22. BEDO DRAM, Read Cycle
A
1
D
D
D
D
Tr
S_CLK
RAS#
MA[11:0]
ROW
COL
COL
COL
COL
WRITE CAS#
AD[31:0]
ADDR
D OUT
D OUT
D OUT
D OUT
Figure 23. BEDO DRAM, Write Cycle
ADVANCE INFORMATION
53
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TD
TD
TD
TD
TR
CE[1]#
MA[11:0]
ADDR
ADDR ADDR ADDR
MWE[3:0]#
AD[31:0]
ADDR
D IN
D IN
D IN
D IN
Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States
TA S_CLK
TD
TD
TD
TD
TR
CE[1]#
MA[11:0]
ADDR
ADDR ADDR ADDR
MWE[3:0]#
AD[31:0]
ADDR
D OUT
D OUT
D OUT
D OUT
Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States
54
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
5.0
BUS FUNCTIONAL WAVEFORMS
TA S_CLK TD TR TI TI TA TD TR TI TI
AD31:0
ADDR
D In
Invalid
ADDR
D In
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus
ADVANCE INFORMATION
55
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TD
TD
TR
TA
TD
TD
TD
TD
TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus
56
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TW
TW
TD
TW
TD
TW
TD
TW
TD
TR
AD31:0
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS#
BE3:0#
WIDTH1:0
10
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus
ADVANCE INFORMATION
57
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TD
TD
TR
TA
TD
TD
TD
TD
TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
DATA Out
DATA Out
ALE
ADS#
BE1/A1# BE0/A0#
00 or 10
01 or 11
00
01
10
11
WIDTH1:0
00
00
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus
58
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TW
TD
TD
TR
TR
TA
TW
TD
TD
TR
AD31:0
ADDR
D In
D In
ADDR
DATA Out
DATA Out
ALE
ADS#
BE1/A1#
0
1
0
1
BE3# BE0#
WIDTH1:0
01
01
D/C#
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Figure 30. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus
ADVANCE INFORMATION
59
I960(R) Rx I/O Processor at 3.3 V
TA S_CLK
TD
TR
TA
TD
TR
TA
TD
TR
TA
TD
TR
AD31:0
A
D In
A
D In
A
D In
A
D In
ALE
ADS#
BE3:0#
1101
0011
0000
1110
WIDTH1:0
10
D/C#
Valid
W/R#
BLAST#
DT/R#
DEN#
LRDYRCV# RDYRCV#
Figure 31. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus
60
ADVANCE INFORMATION
I960(R) Rx I/O Processor at 3.3 V
TI or TR
TH
TH
TI or TA
S_CLK
Outputs: AD31:0, ALE, ADS#, BE3:0# D/C#/RSTMODE# LRDYRCV#, FAIL# WIDTH/HLTD1, WIDTH/HLTD1/RETRY, W/R#, DT/R#, DEN#, BLAST#, LOCK#/ONCE#
Valid
Valid
HOLD
HOLDA
(Note)
NOTE: HOLD is sampled on the rising edge of S_CLK. HOLDA is granted after the latency counter in the local bus arbiter expires. The processor asserts HOLDA to grant the bus on the same edge in which it recognizes HOLD if the last state was Ti or the last Tr of a bus transaction. Similarly, the processor deasserts HOLDA on the same edge in which it recognizes the deassertion of HOLD.
Figure 32. HOLD/HOLDA Waveform For Bus Arbitration
ADVANCE INFORMATION
61

S_CLK
I960(R) Rx I/O Processor at 3.3 V
ADS#, BE3:0# BLAST#, DEN# LRDYRCV

P_RST#

LOCK#/ ONCE#
(Input)

Figure 33. 80960 Core Cold Reset Waveform

1 ms power and clock stable
V and S_CLK stable to P_RST# High, minimum CC 100 s for PLL stabilization.

Valid
STEST

Valid (Output)
D/C#/RST_MODE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY

AD31:0
Idle (Note 2)
FAIL#

(Note 1)
ALE, DT/R#, HOLD, HOLDA, W/R#

VCC

62
Built-in self test approximately 414,000 S_CLK periods (if selected) First Bus Activity
Notes: 1. The processor asserts FAIL# during built-in self-test. If self- test passes, the FAIL# is deasserted.The processor also asserts FAIL# during the bus confidence test. If the bus confidence test passes, FAIL# is deasserted and the processor begins user program execution.
ADVANCE INFORMATION
2. If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure.
ADS#, BE3:0#,DEN#, BLAST#, D/C#/RST_MODE#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY,LRDYRCV#

FAIL# AD31:0 HOLD
LOCK#/ONCE# STEST

S_RST#, P_RST# Maximum L_RST# Low to Reset State 4 S_CLK Cycles L_RST#

Minimum L_RST# Low Time 16 S_CLK Cycles NOTE: Local bus warm reset occurs when Bit 5 in the Extended Bridge Control Register (EBCR) is set; L_RST# asserts when all ATU and/or DMA activity ceases on the PCI buses. L_RST# asserts in a mimimum of 18 clock cycles after EBCR bit 5 is set.
I960(R) Rx I/O Processor at 3.3 V
L_RST# High to First Bus Activity, 46 S_CLK Cycles

Figure 34. 80960 Local Bus Warm Reset Waveform
HOLDA
Valid

ADVANCE INFORMATION
S_CLK
ALE, W/R#,DT/R#
63
I960(R) Rx I/O Processor at 3.3 V
6.0
DEVICE IDENTIFICATION ON RESET
During the manufacturing process, values characterizing the I960 Rx I/O processor type and stepping are programmed into the memory-mapped registers. The I960 Rx I/O processor contains two read-only device ID MMRs. One holds the Processor Device ID (PDIDR - 0000 1710H) and the other holds the I960 Core Processor Device ID (DEVICEID - FF00 8710H). During initialization, the PDIDR is placed in g0. The device identification values are compliant with the IEEE 1149.1 specification and Intel standards. Table 32 describes the fields of the two Device IDs. Table 32. Processor Device ID Register - PDIDR
31 LBA 28 24 20 16 12 8 4 0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
LBA: PCI:
1710H NA
Legend: NA = Not Accessible RO = Read Only RV = Reserved PR = Preserved RW = Read/Write RS = Read/Set RC = Read Clear LBA = 80960 Local Bus Address PCI = PCI Configuration Address Offset Description Version - Indicates stepping changes. VCC - Indicates device voltage type. 0 = 5.0 V 1 = 3.3 V Product Type - Indicates the generation or "family member". Generation Type - Indicates the generation of the device. Model Type - Indicates member within a series and specific model information. Manufacturer ID - Indicates manufacturer ID assigned by IEEE. 0000 0001 001 = Intel Corporation Constant
Bit 31:28 27
Default X X
26:21 20:17 16:12 11:01 0
X X X X 1
NOTE: Values programmed into this register vary with stepping. Refer to the I960(R) Rx I/O Processor Specification Update (272918) for the correct value.
64
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